(General Background Art)
Thanks to recent developments in miniaturization, liquid in crystal materials, high density packaging techniques and others, various types of image display devices (e.g., televisions that employ a liquid crystal panel having a diagonal line length of 5 to 50 cm) are Ad presently manufactured and marketed on a large scale. Further, color displaying is easily enabled by forming red, green and blue colored layers on either one of two glass substrates that constitute a liquid crystal panel. This tendency is noticeable particularly in the so-called active type liquid crystal panels having a switching element for every pixel, because they have less crosstalk and capability of displaying high contrast images at high response speed.
While the matrix structures of image display devices (liquid crystal panels), which employ such liquid crystals, generally include 200 to 1,200 scan lines and about 200 to 1,600 signals lines, techniques for achieving larger screens and higher refinement (i.e., higher pixel densities and higher gray scales) concurrently progress in order to meet demands toward higher displaying quality.
FIG. 1 shows the condition of each part mounted in a liquid crystal panel. As shown in FIG. 1, specified electric signals or picture signals are provided for an image displaying section by the COG (Chip-On-Glass) process or the TCP (Tape-Carrier-Package) process. The COG process is used for, for example, connection of a semiconductor integrated circuit chip 3 by use of a conductive adhesive, the semiconductor integrated circuit chip 3 supplying a drive signal to the electrode terminals 6 of scan lines formed on one of transparent insulating substrates (i.e., glass substrates) 2 that constitutes a liquid crystal panel 1. In the TCP process, for example, a TCP film 4, which is comprised of a thin polyimide type resin film serving as a base and a terminal made of a gold-plated or soldered copper foil (not shown), is pressed against and fixed to the terminals 5 of signal lines, using an appropriate adhesive containing a conductive medium.
While two types of mounting techniques are shown in FIG. 1 for the sake of extensive disclosure of the prior art techniques, it is apparent that either one of them is selected for use in the actual production of display devices.
Reference numerals 7, 8 are wiring lines for connecting the image displaying section positioned at substantially the center of the liquid crystal panel 1 and the electrode terminals 5, 6 of signal lines and scan lines. Reference numeral 9 designates another opposed-glass substrate that serves as a transparent insulating substrate having, on an opposed surface, a transparent conductive opposed electrode common to all liquid crystal cells.
They are not necessarily formed from the same conductive material as that of the electrode terminals 5, 6
FIG. 2 shows an equivalent circuit diagram of an active type liquid crystal panel in which an insulated gate transistor 10 is disposed for every pixel as a switching element. In FIG. 2, reference numerals 8, 7 designate a scan line and a signal line, respectively. Reference numeral 13 designates a liquid crystal cell which is electrically treated as a capacitive element. In this figure, the elements and signal lines depicted by solid line are formed on one (i.e., the substrate on the array side) 2 of the glass substrates which constitute the liquid crystal panel 1 whereas opposed electrodes 14 common to all liquid crystal cells and depicted by dotted line are formed on the other glass substrate (i.e., the opposed substrate) 9.
For the OFF resistance of the insulated gate transistor 10, or where the resistance of the liquid crystal cell is low, or where importance is attached to the gray scale of displayed images, some devices are made to the circuit. For instance, an auxiliary storage capacitor 15 is added in parallel with each liquid crystal cell 13 in order to increase the time constant of the liquid crystal cell as a load. Note that reference numeral 16 in FIG. 2 is a common bus for the storage capacitors.
FIG. 3 shows a cross section of a fundamental part of a pixel section of a liquid crystal panel. As shown in this figure, the two glass substrates 2, 9, which constitute the liquid crystal panel, are formed so as to be spaced a specified distance (about several μm) apart by use of spacer materials (not shown) such as resin fibers or beads. The gap between them forms a closed space sealed in the periphery of the glass substrate 9 by a sealer made of an organic resin and an end-sealing material (both are not shown). This closed space is filled with a liquid crystal 17 by the vacuum filling method or the like.
For color displaying, an organic thin film, which has a thickness of about 1 to 2 lm and contains either or both of a die and a pigment called a color filter 18, is adhered to the closed space side (i.e., liquid crystal layer side) of the glass substrate 9. In the case of red color displaying for instance, the liquid crystal layer of a red color filter section through which only red light can pass is lit alone, allowing permeation of back light incoming from its rear face. For this arrangement, color filters of red (R), green (G) and blue (B) are arranged in the pattern of mosaic, delta etc. in actual liquid crystal image display devices.
The above-described techniques are already known and therefore a further description of them will be omitted. The glass plate 9 is also called “color filter substrate (CF)”. Depending on the characteristics of the liquid crystal material 17, a polarizing plate 19 is applied to either or both of the upper surface of the glass substrate 9 and the lower surface of the glass substrate 2 so that the liquid crystal panel 1 functions as an electric optical element. Most of currently commercially available liquid crystal panels use TN (Twisted. Nematic) type liquid crystal material and generally require two polarizing plates 19.
Although not shown in the drawings, the permeation type liquid crystal image display device shown in the above figures is exposed to white light projected from a back face light source installed under the liquid crystal image display device. In a reflective type liquid crystal image display device, a reflecting mirror is formed on an array substrate (as a general rule) positioned on the lower side (opposite to the user's side) of the device, a transparent conductive film is formed on the upper side (i.e., the user's side (liquid crystal layer side)) of the reflecting mirror, and a TFT and signals lines are further formed on the conductive film. There are other types of devices such as guest host mode color image displays and multi-layered substrate type image displays.
Reference numeral 20 designates an alignment layer for orienting liquid crystal molecules in a specified direction. The alignment layer is formed on the respective liquid crystal sides of the two glass substrates 2, 9, using a polyimide type resin thin film having a thickness of about 0.1 μm. Reference numeral 21 designates a drain electrode (wiring) for connecting the drain of the insulated gate transistor 10 to a transparent conductive pixel electrode 22. The drain electrode 21 is often formed at the same time with the formation of a signal line (source line) 12. Reference numeral 23 designates a semiconductor layer positioned between the signal line 12 and the drain electrode 21 and will be later described in detail.
Reference numeral 24 is a Cr thin film layer having a thickness of about 0.1 μm and defined by the boundary of a colored layer 18 which abuts on the Cr thin film layer on a color filter 9. The Cr thin film layer 24 functions to prevent external light from coming into the semiconductor layer, the scan lines 11 and the signal line 12, thereby improving color displaying characteristics. Therefore, the Cr thin film layer is generally called “Black Matrix (BM)”.
Next, there will be explained the structure and fabricating process of the insulated gate transistor used as a switching element. Two types of insulated gate transistors have been widely used up to now. One of them is called “etch stop type transistor” which will be described below. FIG. 4 shows a plan view of a unit pixel of an active matrix substrate constituting a conventional liquid crystal panel when it is in a finished condition, whereas FIG. 5 shows transition occurring in the section taken along line A—A as the fabrication process proceeds. Referring mainly to FIG. 5, the fabricating process will be briefly described. A region 48 (the region hatched by rightwardly inclined diagonal lines in FIG. 4), in which a projection 50 formed by the scan lines 11 and the pixel electrode 22 are overlapped with each other with a gate insulating layer between, forms the aforesaid storage capacitor 15, but a detailed description of it is omitted herein.
Now, reference is made to FIG. 5.
(1) As an insulating substrate having high heat resistance, chemical resistance and transparency, a 0.5 to 1.1 mm-thick glass substrate 2 (e.g., “product 1737” produced by Corning Co., Ltd.) is used. Cr, Ta, Mo or the like or an alloy of these metals is applied to one surface of the glass substrate 2 by use of a vacuum film formation system such as SPT (sputtering system), thereby forming a first metal layer having a thickness of about 0.1 to 0.3 μm. Then, a gate electrode 11 also serving as a scan line is “selectively” formed (i.e., formed on only a predetermined position) on one surface of the glass substrate 2 by the elaborative processing technique such as photolithography.
It is preferable to use aluminum (AL) as the material of the scan lines in order to reduce the resistance value of the scan lines for coping with the trend toward larger screens for liquid crystal panels. Since AL is low in heat resistance, AL is used by laminating it with one of the above-mentioned heat-resistant metals Cr, Ta, Mo and their silicides, or alternatively by forming an anodized layer (AL2O3) on the surface of AL by anodic oxidation. In short, the scan lines 11 are generally comprised of a plurality of metal layers or the like.
(2) Three kinds of thin film layers, which are (i) a first SiNx (silicon nitride) layer 30 serving as a gate insulating layer, (ii) a first amorphous silicon (a-Si) layer 31 which contains virtually no impurities and serves as a channel for an insulated gate transistor, and (iii) a second SiNx layer 32, are sequentially formed on the entire surface of the glass substrate 2 so as to have thicknesses of about 0.3 μm, 0.05 μm, and 0.1 μm respectively, using a PCVD (Plasma•CVD) system.
Apart from the above, the following yield improvement measures are often taken when the gate insulating layer is formed:                (i) Lamination with other types of insulating layers (e.g., TaOx, SiO2 and Al2O3 mentioned above); and (ii) The two SiNY layers are separately formed and a washing process is carried out in the course of the film formation. It should be noted that the gate insulating layer is not limited to one kind of layer or a single layer. Multi-crystallization (i.e., making polysilicons) by laser-annealing amorphous silicon may be employed. These techniques are already known, and therefore an explanation on them is omitted herein.        
(3) By use of the elaborative processing technique, the second SiNx layer on the gate 11 is “selectively” left (left on a specified position) so as to have width narrower than the gate 11, so that a first amorphous silicon layer 310 is exposed in the form of a so-called island 320. Likewise, a second amorphous silicon 330 containing, for example, phosphorus as an impurity and having a thickness of about e.g., 0.05 μm is applied to the entire surface, using the PCVD system.
The gate insulating layer 30 is exposed, with the islands 310, 320 of the first and second amorphous silicon layers being left only in the vicinity of the gate 11.
(4) An ITO (Indium-Tin-Oxide) for example is applied as a transparent conductive layer having a thickness of about 0.1 to 0.2 μm, using a vacuum film formation system such as SPT (sputtering system), and the pixel electrode 22 is formed by the elaborative processing technique.
Although not shown in the drawings, selective formation of an opening necessary for electric connection to the scan lines 11 is carried out, the opening leading to the gate insulating layer 30 formed on the scan lines in the periphery of the image displaying section.
(5) By use of a vacuum film formation system such as SPT, a heat-resistant metallic thin film layer made from e.g., Ti, Cr or Mo is formed as a heat-resistant metal layer having a thickness of about 0.1 μm and, subsequently, an AL thin film layer having a thickness of about 0.3 μm is formed as a low-resistant wiring layer. Then, the drain electrode 21 of the insulated gate transistor composed of a lamination of a heat-resistant metal layer 340 and a low-resistant wiring layer 350 and the source electrode 12 serving as a signal line as well are selectively formed by the elaborative processing technique. By use of a photosensitive resin pattern used in the selective pattern formation as a mask, the amorphous silicon layer 330 on the second SiNx layer 320 between the source and drain electrodes is removed to expose the second SiNx layer 320, while the first amorphous silicon layer 310 in other areas is removed to expose the gate insulating layer 30.
The source electrode 12 and the drain electrode 21 are formed in such a positional relationship that they are partly overlapped with the gate 11 in a plane, so that the insulated gate transistor does not have an offset structure. There are other common designs. For example, an opening is formed on the scan lines 11 in the periphery of the image displaying section and the terminal electrode 6 on the side of the scan lines is formed simultaneously with the signal line 12, or a wire line 8 for connecting the scan lines 11 to the terminal electrode 6 on the scan line side is formed.
Lastly, like the formation of the gate insulating layer 30, a 0.3 to 0.7 μm-thick SiNx layer is applied to the entire surface of the glass substrate 2 as a transparent insulating layer, using the PCVD system, so that a passivation insulating layer is formed.
(6) An opening 38 is formed on the pixel electrode 22 to expose most part of the pixel electrode 22, while an opening (not shown) is formed on the terminal electrodes 5, 6 in the periphery thereby to expose most part of the terminal electrodes 5, 6. Thus, formation of the active substrate 2 is completed.
If the resistance of the signal line 12 does not cause a problem for such a reason that the size of the display panel is small, the low-resistant wiring layer made of AL is not always necessary and a heat-resistant metal material such as Cr, Ta or Mo is used, so that the source wiring 12 and the drain wiring 21 can be formed into a single layer.
The details of the heat resistance of insulated gate transistors are described in the previous example, Japanese Patent Publication Gazette No. 7-74368 (1995). Apart from the above, there are other steps such as filling of impurities, but this is a known technique and therefore its explanation will be omitted.
The passivation insulating layer 37 on the pixel electrode 22 is removed for the following reasons: firstly, the effective voltage applied to the liquid crystal cell is prevented from dropping. Secondly, since the quality of the passivation insulating layer is usually extremely poor, such an unfavorable situation must be avoided that electric charges are accumulated within the passivation insulating layer resulting in the persistence of displayed images. This is due to the fact that the heat resistance of the insulated gate transistor is not satisfactorily high and therefore the temperature of F=the formation of the passivation insulating layer is inevitably 250° C. or lower which is several (abt. 5, 6) tens of degrees centigrade lower than that of the gate insulating layer.
Next, there will be explained liquid crystal panels of Parallel Electric Field Mode or IPS (In-Plane Switching) Mode which are recently extensively commercialized because of their capability of displaying with wide viewing angles. FIG. 6 shows a cross section of a fundamental part of the image displaying section of an IPS mode liquid crystal panel. This IPS mode liquid crystal panel differs from the conventional prevailing liquid crystal panel shown in FIG. 3 in that the liquid crystal cell is composed of opposed conductive electrodes 40 and a pixel electrode 41(21) which are spaced a specified distance apart and a liquid crystal 17, and that the liquid crystal 17 is switched (operated) by the parallel-oriented electric field generated between the opposed electrodes 40 and the pixel electrode 41. Therefore, in the IPS mode liquid crystal panel, there is no need to provide a transparent conductive opposed electrode on the color filter substrate and to provide a transparent conductive pixel electrode on the active substrate. This leads to a reduction in the number of steps for fabricating the active substrate.
FIG. 7 shows a plan view of a unit pixel of the active substrate of the IPS mode liquid crystal panel. FIG. 8 shows transition in the cross section taken along line A—A of FIG. 7, which occurs with the progress of the fabrication process. Referring mainly to FIG. 8, the fabrication process of an IPS mode liquid crystal panel will be hereinafter briefly described, taking a case, in which a channel etch type insulated gate transistor is employed, for example. In FIG. 7, the region. 49 (doubled hatched region), in which the opposed electrodes (common capacitance lines) 40 and the pixel electrode 41(21) are partially overlapped with each other, with the gate insulating layer between, forms a storage capacitor 15, but this will not be explained in detail herein.
Reference is now made to FIG. 8.
(1) A first metal layer having a thickness of about 0.1 to 0.3 μm is applied to one surface of the glass plate 2, using a vacuum film formation system such as SPT (sputtering system) and the gate electrode 11 which also function as scan lines and the opposed electrodes 40 are selectively formed by the elaborative processing technique.
(2) Three kinds of thin film layers, which are (i) the first SiNx layer 30 serving as a gate insulating layer, (ii) the first amorphous silicon layer 31 which contains virtually no impurities and serves as a channel for the insulated gate transistor, and (iii) the second amorphous layer 33 which contains impurities and serves as a source and drain for the insulated gate transistor, are sequentially formed on the entire surface of the glass substrate 2 so as to have thicknesses of about 0.3 μm, 0.2 μm, and 0.05)μm respectively, using the PCVD (Plasma CVD) system.
(3) The gate insulating layer 30 is exposed, with first and second semiconductor layers made of amorphous silicon left as islands 310, 330 on the gate 11. Although not shown in the drawings, selective formation of an opening is done, the opening leading to the gate insulating layer 30 on the scan lines around the image displaying section. This opening is required for electric connection to the scan lines 11.
(4) By use of a vacuum film formation system such as SPT, a Ti thin film layer for instance is formed as a heat-resistant metal layer having a thickness of about 0.1 μm and, subsequently, an AL thin film layer having a thickness of about 0.3 μm is formed as a low-resistant wiring layer. Then, the drain electrode 21 and source electrode 12 for the insulated gate transistor are selectively formed, using the elaborative processing technique, the drain electrode 21 serving as the pixel electrode 41 as well while the source electrode 12 serves as a signal line as well. This selective pattern formation is called “channel etch” because the AL thin film layer 350, the Ti thin film layer 340 and the second amorphous silicon layer 330 are sequentially etched, using, as a mask, a photosensitive resin pattern 43 used in the formation of the source and drain wiring and the first amorphous silicon layer 310 is etched with a part (0.05 to. 0.1 μm in height) being left.
(5) After the photosensitive resin pattern 43 has been removed, a 0.3 μm-thick SiNx layer is applied to the entire surface of the glass substrate 2 as a transparent insulating layer using the PCVD system similarly to the formation of the gate insulating layer, whereby a passivation insulating layer 37 is formed. Although not shown in the drawings, an opening is formed on the terminal electrodes around the periphery of the substrate to expose most part of the terminal electrodes 5, 6. Thus, the formation of the active substrate is completed.
It is apparent from the above description that since the opposed electrodes 40 are formed simultaneously with the formation of the scan lines 11 while the pixel electrode 41 is formed simultaneously with the formation of the source and drain wires 12, 21, the transparent conductive layer 22 serving as the pixel electrode is unnecessary and as a result, the number of fabricating steps can be reduced, compared to the fabrication process described earlier.
It is necessary for channel etch type insulated gate transistors in view of the uniformity of the film formation process and the etching process to make the first amorphous silicon layer including no impurities thicker than those of etch stop type transistors. Regarding the operation of the PCVD system and particle generation, the channel etch type has a problem in production capability. In addition, it has a problem in performance index since the mobility of electrons is small. These subjects will not be further discussed herein.
(Background art in view of the problems that the invention is to solve)
As understood from the foregoing description, the fabrication of active type liquid crystal image displays is quite complicated and requires high precision. Therefore, defects inevitably occur in various modes. To solve this problem, various inspections, estimations and tests are made in accordance with the quality standard at the time of shipment from plants. As a result, defect modes such as checked and dealt with in the various inspections are rarely found by the end users or consumers and rarely cause damage nor troubles to them. However, some defect modes occur after long-run jobs or long use, although it is always the case with other products. To cope with such defect modes, absence of defects must be confirmed by making an aging inspection in which products undergo a so-called accelerated test environment such as a highly heated condition. This aging inspection is not so expensive when conducted on a certain production lot, but incurs tremendous cost when all products are tested for more than several hours.
A typical defect mode which requires the above aging inspection will be described, taking a case for example in which black-dot-like stains are growing rapidly after long use in a liquid crystal image display device which naturally displays white images (the stains could be white-dot-like etc. stains in black displaying mode or color displaying mode).
This defect mode occurs only when there is a minute pinhole 44 having a size of 1 μm or less on the insulating layer as shown in FIG. 9 which illustrates a cross section taken along line B—B of FIGS. 4 and 7. The insulating layer exists on the scan lines 11 abutting the liquid crystal 17 and is composed of the gate insulating layer 30 and the passivation insulating layer 37. Occurrence of such a pinhole is often caused by inclusion of minute foreign matters or particles during the formation of the insulating layer used for fabricating the active substrate 2 and impossible to be prevented with the current technology. It is also difficult to prevent occurrence of pinholes in a photosensitive resin during the photolithography process which is repeated several times. Dust generated particularly in the gate insulating layer is unavoidable because of the characteristics of the PCVD system, so that pinholes are likely to occur in the gate insulating layer.
Generally, the passivation insulating layer 37 is formed on the entire surface of the active substrate 2. Therefore, even if a pinhole of 1 μm or more is present in the gate insulating layer, it is covered with the passivation insulating layer 37 so that the scan lines 11 and the opposed electrodes 40 are not exposed. The resolution of photolithography for forming the opening 38 in the passivation insulating layer 37 is less than 1 μm so that there is virtually no fear of occurrence of pinholes having a size of 1 μm or less during the formation of the opening in the passivation insulating layer 37.
However, the ordinary passivation insulating layer made of SiNx is poor in coverage because it is formed at low temperature as described earlier. Therefore, if a pinhole of 1 μm or less is present in the gate insulating layer 30, a minute hole 44 is sometimes formed in the passivation insulating layer 37 as shown in FIG. 9. In this case, the scan lines 11 and the opposed electrodes 40 are partially exposed (It should be noted that if a pinhole of 1 μm or more has occurred in the gate insulating layer 30, the pinhole is filled up with the passivation insulating layer 37 so that the aforesaid defect mode will not occur).
As mentioned earlier, there is formed the alignment layer 20 having a thickness of about 0.1 μm on the opposed electrodes 14, and pinholes are likely to occur in this alignment layer since the opposed electrodes 14 have a large area. The scan lines 11 of the active liquid crystal panel are usually continuously supplied with a potential of 0 to minus (−) several volts so that a direct current potential is always applied between the scan lines 11 and the opposed electrodes 14 (an ordinary TN type liquid crystal panel) or 40 (an IPS type liquid crystal panel). This causes the liquid crystal in the vicinity of the pinhole 44 to be degraded by hydrolysis and as a result, the color of displayed images, which should be white, becomes brown and then black. This is the cause of the above-described defect mode.
In short, if a pinhole having a size of 1 lm or less is present in the gate insulating layer, the pinhole is not filled up with the passivation insulating layer so that it is impossible to prevent occurrence of defects.
The pinhole is minute, having a size of 1 μm or less, the liquid crystal does not degrade before several hours to several days are past even if it is heated to about 60° C., being in an accelerated condition. Therefore, when an aging inspection is made to check such a liquid crystal, there is imposed a serious burden. The aging inspection takes a long time particularly in the case of IPS mode liquid crystal panels because the opposed electrodes of the IPS mode have a smaller area, compared to those of TN mode liquid crystal panels so that current does not flow smoothly.
Even when a pinhole inspection is done with the most up-to-date automatic optical inspection system in the fabrication process in order to solve the above problem, the currently available resolving power is insufficient (the resolution prescribed by the specification is 1.5 μm). It can be easily imagined that even if a high resolving power optical inspection system was available, it would take more than several minutes to inspect one active substrate, and as a result, the inspection cost would be forced to increase tremendously.
As an effective measure for preventing occurrence of pinholes of 1 μm or less, there has been proposed a technique in which the passivation insulating layer is formed so as to be as thick as 1 μm and the pinholes are filled up with the passivation insulating layer per se. However, this leads to an increase in the cost of the passivation insulating layer formation process. Another conceivable attempt is such that the formation temperature of the passivation insulating layer is raised to about 300° C. to improve the coverage of the passivation insulating layer, but this also reveals a drawback. Concretely, where the semiconductor layer is a-Si, it has low heat resistance so that the mobility μ of electrons becomes lower, causing degradation of the electric characteristics of the insulated gate transistor. In consequence, difficulties arise in the application of lug the insulated gate transistor to large-screen or high precision liquid crystal panels.
For applying electrochemical treatment such as anodic oxidation to the substrate, the following process is needed: As shown in FIG. 10, the substrate 2 is immersed in a formation solution 51 in an insulated vessel 50, being hold in an upright condition. A direct current potential is then applied to a connection pattern 52 formed on the upper part of the substrate 2 through a connection jig such as clips, with the upper part of the substrate 2 being partly left above the surface of the solution. In FIG. 10, reference numerals 53, 54, 55 designate a direct current power source, an ammeter and a cathode plate composed of an SUS plate, respectively.
The above process has revealed the following problem. The size of the substrate, which is presently 550×650 mm, is expected to be 600×720 mm in the next generation and to further increase to 850×950 mm. If the substrate becomes larger, the height of the anodic oxidation system must exceed 3 m because of the increased size of the mechanism for vertically lifting and lowering the substrate. Therefore, a significant number of steps are needed for delivery and installation in a plant and in addition, this requires a clean room with a high ceiling, accompanied with the increased capacity of the clean room and therefore increased air conditioning cost. Also, treatment systems, which deal with chemical solutions, have a cost problem in the maintenance of the clean room, because there is a high possibility of generation of a large amount of chemical mist so that a large amount of air needs to be exhausted for the sake of security and hygiene.
As has been described above, it is difficult to cover the conductive pattern on the substrate with an insulating layer free from pinholes and such pinholes are likely to be the main cause of various defects particularly in the substrate of display devices.
In such circumstances, there have been long awaited the realization of a pinhole test method capable of detecting pinholes on scan lines, opposed electrodes and storage capacitance lines without conducting an aging inspection. For accomplishing the above and other objects, there have been strong demands to the development of a compact production system capable of applying electrochemical treatment to a particular region in a substrate, applying electrochemical treatment to a plurality of substrates at the same time, and dealing with larger substrates.